tag:blogger.com,1999:blog-3888382143307542639.post6043411606118646947..comments2023-02-02T03:36:20.483+00:00Comments on Lacking Rhoticity: L3 cache mapping on Sandy Bridge CPUsMark Seabornhttp://www.blogger.com/profile/08046205947658697263noreply@blogger.comBlogger2125tag:blogger.com,1999:blog-3888382143307542639.post-85038299853716467582015-07-04T01:16:49.313+01:002015-07-04T01:16:49.313+01:00It looks like bit 32 should be included in the set...It looks like bit 32 should be included in the set of physical address bits that are XOR'd together. Also, there was a bias in the test program I linked to. For more info, see <a href="https://groups.google.com/d/msg/rowhammer-discuss/k-Ivz4DJ3s4/cLgl5D_HMf0J" rel="nofollow">this post</a>.Mark Seabornhttps://www.blogger.com/profile/08046205947658697263noreply@blogger.comtag:blogger.com,1999:blog-3888382143307542639.post-38812695121078755772015-05-07T18:18:53.647+01:002015-05-07T18:18:53.647+01:00Note that another term for this distributed ring-b...Note that another term for this distributed ring-based cache appears to be "Non-Uniform Cache Architecture" (NUCA), presumably by analogy with <a href="http://en.wikipedia.org/wiki/Non-uniform_memory_access" rel="nofollow">Non-Uniform Memory Access/Architecture</a> (NUMA).<br /><br />The term is mentioned in this 2011 blog post: "<a href="http://utaharch.blogspot.com/2011/08/debate-over-shared-and-private-caches.html" rel="nofollow">The Debate over Shared and Private Caches</a>" (Utah Arch blog).<br /><br />I've not seen the term NUCA used in connection with Sandy/Ivy Bridge, but that's presumably just because the details of these CPUs' cache architectures and their research origins don't get discussed very often.Mark Seabornhttps://www.blogger.com/profile/08046205947658697263noreply@blogger.com