Monday, 8 January 2018

Observing interrupts from userland on x86

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In 2016, I noticed a quirk of the x86 architecture that leads to an interesting side channel. On x86, it is possible for a userland process...
1 comment:
Tuesday, 20 October 2015

PassMark received offer to not release rowhammer test

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Here's an interesting report of skulduggery related to the rowhammer bug . PassMark say they received an offer to not release a rowha...
Sunday, 24 May 2015

Passing FDs/handles between processes on Unix and Windows -- a comparison

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Handles on Windows are analogous to file descriptors (FDs) on Unix, and both can be passed between processes. However, the way in which ha...
3 comments:
Monday, 11 May 2015

Can cached memory accesses do double-sided row hammering?

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There are indications that it is possible to cause bit flips in memory by row hammering without using CLFLUSH , using normal cached memory...
Monday, 4 May 2015

How physical addresses map to rows and banks in DRAM

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In my previous blog post , I discussed how Intel Sandy Bridge CPUs map physical addresses to locations in the L3 cache. Now I'll disc...
1 comment:
Monday, 27 April 2015

L3 cache mapping on Sandy Bridge CPUs

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In 2013, some researchers reverse-engineered how Intel Sandy Bridge CPUs map physical addresses to cache sets in the L3 cache (the last-le...
2 comments:
Tuesday, 10 March 2015

The DRAM rowhammer bug is exploitable

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I've been researching the DRAM rowhammer issue and its security implications for a while. We've finally published our findings on ...